A critical part in a microcontroller system is program execution, which should never be out of control. Many deficiencies or unexpected situations can be successfully managed by protection or secure system control functions as for example the use of watchdog circuits. A critical situation which can not be handled by a watchdog circuit occurs if parts or all of the system fail to comply with the system clock frequency. In this situation a slave memory may not be able to deliver the data on time without corrective action. The system will most likely fail. A master such as a central processing unit (CPU) is driven by a system clock. A data bus connects the master and slaves. The slaves are typically memories or peripheral modules. The instruction memory is usually a flash or read only memory (ROM). The data memory is typically random access memory (RAM). However, a program may also be executed from RAM. The timing for transferring any kind of data including instructions or data relating is based on the system clock frequency. If a slave is too slow, data may not be delivered to the master in time. Inherent data bandwidth or speed limitations and many other implications may cause a delay of the data transfer from a slave to a master. This results in incomplete or incorrect received data. A conventional way to ensure that the maximum frequency of the system clock is not too high for the components of the system sets a predetermined maximum frequency or a set of safe-area-off-operation parameters is given. These parameters must be met by the user. Other solutions use a reference measurement to control the maximum clock frequency. This maintains a reliable system clock. Most of the prior art solutions rely on a system level control mechanism which sets the frequency of the system clock to comply with the slowest component or with a critical path with the maximum delay. This limits the overall data or program throughput by the slowest component or the critical path. Thus the system may not achieve maximum performance. Another conventional approach introduces wait states for a slow slave which requires more response time. This allows a comparably high clock frequency to be used for the reminder of the system except for those parts needing wait states. Timing parameters and the number of wait states has to be determined based on the worst-case electrical characteristics of the slave. Accordingly, a prior art electronic device including a master and slave will hardly ever achieve maximum performance.